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1 ds05-12101-2e fujitsu semiconductor data sheet memory cmos 2 128k 32 synchronous gram mb81g83222-010/-012/-015 cmos 2 banks of 131,072-words 32-bit synchronous graphic random access memory n description the fujitsu mb81g83222 is a cmos synchronous graphic random access memory (sgram) containing 8,388,608 memory cells accessible in an 32-bit format. the mb81g83222 features a fully synchronous operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. the mb81g83222 sgram is designed to reduce the complexity of using a standard dynamic ram (dram) which requires many control signal timing constraints, and may improve data bandwidth of memory as much as 5 times more than a standard dram. the mb81g83222 is ideally suited for graphics workstations, laser printers, high resolution graphic adapters, accelerators and other applications where an extremely large memory and bandwidth are required and where a simple interface is needed. n absolute maximum ratings (see note) note: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameters symbol value unit voltage of v cc supply relative to v ss v cc , v ccq ?.5 to +4.6 v voltage at any pin relative to v ss v in , v out ?.5 to +4.6 v short circuit output current i out 50 ma power dissipation p d 1.2 w storage temperature t stg ?5 to +125 c this device contains circuitry to protect the inputs against damage due to high static voltages or electric ?lds. however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
2 mb81g83222-010/mb81g83222-012/MB81G83222-015 n product line & features n package parameter mb81g83222-010 mb81g83222-012 MB81G83222-015 clock frequency 100 mhz max. 84 mhz max. 67 mhz max. burst mode cycle time 10 ns min. 12 ns min. 15 ns min. ras access time 58 ns max. 67 ns max. 75 ns max. cas access time 28 ns max. 32 ns max. 35 ns max. access time from clock (cl=3) 9 ns min. 11 ns min. 12 ns min. operating current (two banks active) 280 ma max. 245 ma max. 210 ma max. power down mode current 2 ma max. single +3.3v supply 10% tolerance lvttl compatible i/o 1,024 refresh cycles every 16.4 ms dual bank operation byte control by dqm 0 to dqm 3 burst read/write operation and burst read/single write operation capability programmable burst type, burst length, and cas latency 8 column block write function write per bit function (old mask) auto-and self-refresh cke power down mode output enable and input data mask fpt-100p-m15 package and ordering information ?100-pin plastic qfp, order as mb81g83222- pq plastic qfp package marking side
3 mb81g83222-010/mb81g83222-012/MB81G83222-015 n pin assignments and descriptions v cc , v ccq dq 0 to dq 31 v ss , v ssq dqm 0 to dqm 3 we cas ras cs ap a 0 to a 7 , a 8 nc cke clk supply voltage data i/o ground input/output mask write enable column address strobe chip select address input row :a 0 to a 8 column :a 0 to a 7 (a 8 =ap) auto precharge enable no connection clock enable clock input row address strobe dsf special function enable a 9 (ba) bank select symbol description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 dq1 dq0 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc 100-pin qfp dq 3 v ccq dq 4 dq 5 v ssq dq 6 dq 7 v ccq dq 16 dq 17 v ssq dq 18 dq 19 v ccq v cc v ss dq 20 dq 21 v ssq dq 22 dq 23 v ccq dqm 0 dqm 2 we cas ras cs a 9 (ba) nc dq 28 v ccq dq 27 dq 26 v ssq dq 25 dq 24 v ccq dq 15 dq 14 v ssq dq 13 dq 12 v ccq v ss v cc dq 11 dq 10 v ssq dq 9 dq 8 v ccq nc dqm 3 dqm 1 clk cke dsf nc a 8 /ap v v cc (top view) dq2 ssq v ss dq 31 dq 30 v ssq dq 29 a 0 a 1 a 2 a 3 v cc v ss a 4 a 5 a 6 a 7
4 mb81g83222-010/mb81g83222-012/MB81G83222-015 fig. 1 - mb81g83222 block diagram bank-1 v cc / v ccq clk cke a 0 to a 9 dq 0 to dq 31 command decoder clock buffer address buffer/ register & bank select i/o data buffer/ register control signal latch mode register column address counter ras cas we dram core (512 256 32) col. addr. ras cas we cs bank-0 i/o row addr. to each block v ss / v ssq color register mask register dqm 0 to dqm 3 dsf
5 mb81g83222-010/mb81g83222-012/MB81G83222-015 n function truth table command truth table notes:1. v = valid, l = logic low, h = logic high, x = either l or h. 2. all commands assumes no csus command on previous rising edge of clock. 3. all commands are assumed to be valid state transitions. 4. all inputs are latched on the rising edge of clock. 5. nop and desl commands have the same effect on the part. 6. bst command is effective only during full column burst read or write. 7. read, reada, writ, writa, bwrit, and bwrita commands should only be issued after the cor- responding bank has been activated (actv or actvm command). refer to state diagram. 8. actv and actvm commands should only be issued after corresponding bank has been precharged (pre or pall command). 9. required after power up. 10. mrs command should only be issued after all banks have been precharged (pre or pall command). refer to state diagram. function notes symbol cke cs ra s ca s we dsf a 9 a 8 a 7 -a 0 n-1 n device deselect 5 desl h x h xxxxxx x no operation 5 nop h x l h h h x x x x burst stop 6 bst h x l h h l l x x x read 7 read h x lhlhlvl v read with auto-precharge 7 reada h x lhlhlvh v write 7 writ h x l h l l l v l v write with auto-precharge 7 writa h x l h l l l v h v block write 7 bwrit h x l h l l h v l v block write with auto-precharge 7 bwrita h x l h l l h v h v bank active (ras) & wpb disable 7 actv h x l l h h l v v v bank active (ras) & wpb enable 8 actvm h x l l h h h v v v precharge single bank pre h x l l h l l v l x precharge all banks pall h x l l h l l x h x mode register set 9, 10 mrs h x lllllvl v special mode register set smrs h x llllhll v
6 mb81g83222-010/mb81g83222-012/MB81G83222-015 n functional truth table (continued) dqm truth table notes:1. i=0, 1, 2, 3. 2. dqm 0 for dq 0 to 7 , dqm 1 for dq 8 to 15 , dqm 2 for dq 16 to 23 , dqm 3 for dq 24 to 31 . cke truth table notes:1. the csus command requires that at least one bank is active. refer to state diagram. 2. ref and self commands should only be issued after all banks have been precharged (pre or pall command). refer to state diagram. 3. pd command should be issud after all banks have been precharged (pre or pall command). if a bank or all banks are in active state, pd command can be issued in conjuction with pre or pall com- mand whichever precharge command makes all banks in idle state. function symbol cke dqmi n-1 n i-th byte write enable / output enable enbi h x l i-th byte data mask / output disable maski h x h current state function note s sym- bol cke cs ra s ca s we dsf a 9 (ba ) a 8 (ap ) a 7 0 n-1 n bank active clock suspend mode entry 1 csus h l xxxxxxxx any clock suspend continue 1 l l xxxxxxxx clock suspend clock suspend mode exit l h xxxxxxxx idle auto-refresh command 2 ref h h l l l h l x x x idle self-refresh entry 2 self h l l l l h l x x x self refresh self-refresh exit self x lhlhhhxxxx lhhxxxxxxx idle power down entry pd hllhhhxxxx hlhxxxxxxx prechatge power down entry pd hllhhhxxxx hlhxxxxxxx back active power down entry 3 pd hlllhllvlx hlllhllxhx power down power down exit lhlhhhxxxx lhhxxxxxxx
7 mb81g83222-010/mb81g83222-012/MB81G83222-015 n functional truth table (continued) operation command table (aplicable to single bank) current state cs ra s ca s we ds f addr command function notes idle h xxxx x desl nop l h h h x x nop nop l h h l l x bst nop lhlhl ba, ca, ap read/reada illegal l h l l l ba, ca, ap writ/writa illegal l l h h l ba, ra actv bank active after t rcd l l h l l ba, ap pre/pall nop l l l h l x ref/self auto-refresh or self-refresh 3 lllll mode mrs mode register set (idle after t rsc ) 3 l l h h h ba, ra actvm bank active & write per bit enable l h l l h ba, ca, ap bwrit/ bwrita illegal llllh special mode smrs special mode register set (idle after t rsc ) bank active h xxxx x desl nop l h h h x x nop nop lhlhl ba, ca, ap read/reada begin read ; determine ap l h h l l x bst nop l h l l l ba, ca, ap writ/writa begin write ; determine ap l l h h l ba, ra actv illegal 2 l l h l l ba, ap pre/pall precharge ; determine precharge type l l l h l x ref/self illegal lllll mode mrs illegal l l h h h ba, ra actvm illegal l h l l h ba, ca, ap bwrit/ bwrita block write ; determine ap llllh special mode smrs special mode register set
8 mb81g83222-010/mb81g83222-012/MB81G83222-015 n functional truth table (continued) operation command table (continued) current state cs ras cas we dsf addr command function notes read h xxxx x desl nop (continue burst to end ? bank active) lhhhx x nop nop (continue burst to end ? bank active) lhhll x bst burst stop ? bank active (bl=full column) nop (bl=1, 2, 4, 8) lhlhl ba, ca, ap read/reada terminate burst, new read ; determine ap l h l l l ba, ca, ap writ/writa terminate burst, start write ; determine ap 4 l l h h l ba, ra actv illegal 2 l l h l l ba, ap pre/pall terminate burst, precharge ; determine precharge type l l l h l x ref/self illegal llllx mode/ special mode mrs/ smrs illegal l l h h h ba, ra actvm illegal 2 l h l l h ba, ca, ap bwrit/ bwrita terminate burst, start block write ; determine ap write hxxxx x desl nop (continue burst to end ? write recovering) lhhhx x nop nop (continue burst to end ? write recovering) lhhll x bst burst stop ? write recovering ? bank active (bl=full column) nop (bl=1, 2, 4, 8) lhlhl ba, ca, ap read/reada terminate burst, start read ; determine ap l h l l l ba, ca, ap writ/writa terminate burst, new write ; determine ap 4 l l h h l ba, ra actv illegal 2 l l h l l ba, ap pre/pall terminate burst, precharge ; determine precharge type 4 l l l h l x ref/self illegal llllx mode/ special mode mrs/ smrs illegal l l h h h ba, ra actvm illegal 2 l h l l h ba, ca, ap bwrit/ bwrita terminate burst, start block write ; determine ap
9 mb81g83222-010/mb81g83222-012/MB81G83222-015 n functional truth table (continued) operation command table (continued) current state cs ras cas we dsf addr command function notes block write hxxxx x desl nop (continue burst to end ? write recovering) lhhhx x nop nop (continue burst to end ? write recovering) l h h l l x bst illegal lhlhl ba, ca, ap read/reada illegal l h l l l ba, ca, ap writ/writa illegal l l h h l ba, ra actv illegal l l h l l ba, ap pre/pall illegal l l l h l x ref/self illegal llllx mode/ special mode mrs/ smrs illegal l l h h h ba, ra actvm illegal l h l l h ba, ca, ap bwrit/ bwrita illegal read with auto precharge hxxxx x desl nop (continue burst to end ? precharge) lhhhx x nop nop (continue burst to end ? precharge) l h h l l x bst illegal lhlhl ba, ca, ap read/reada illegal 2 l h l l l ba, ca, ap writ/writa illegal 2 l l h h l ba, ra actv other bank active, illegal on same bank 2 l l h l l ba, ap pre/pall illegal 2 l l l h l x ref/self illegal llllx mode/ special mode mrs/ smrs illegal l l h h h ba, ra actvm illegal l h l l h ba, ca, ap bwrit/ bwrita illegal
10 mb81g83222-010/mb81g83222-012/MB81G83222-015 n functional truth table (continued) operation command table (continued) current state cs ras cas we dsf addr command function notes write with auto precharge /block write with auto precharge hxxxx x desl nop (continue burst to end ? write recovering with precharge) lhhhx x nop nop (continue burst to end ? write recovering with precharge) l h h l l x bst illegal lhlhl ba, ca, ap read/reada other bank read, illegal on same bank 2 l h l l l ba, ca, ap writ/writa other bank write, illegal on same bank 2 l l h h l ba, ra actv illegal 2 l l h l l ba, ap pre/pall illegal 2 l l l h l x ref/self illegal llllx mode/ special mode mrs/ smrs illegal l l h h h ba, ra actvm illegal 2 l h l l h ba, ca, ap bwrit/ bwrita illegal precharge hxxxx x desl nop (idle after t rp ) l h h h x x nop nop (idle after t rp ) l h h l l x bst illegal lhlhl ba, ca, ap read/reada illegal 2 l h l l l ba, ca, ap writ/writa illegal 2 l l h h l ba, ra actv illegal 2 l l h l l ba, ap pre/pall nop (pall may affect other bank) 5 l l l h l x ref/self illegal llllx mode/ special mode mrs/ smrs illegal l l h h h ba, ra actvm illegal 2 l h l l h ba, ca, ap bwrit/ bwrita illegal
11 mb81g83222-010/mb81g83222-012/MB81G83222-015 n functional truth table (continued) operation command table (continued) current state cs ras cas we dsf addr command function notes bank activating hxxxx x desl nop (bank active after t rcd ) l h h h x x nop nop (bank active after t rcd ) l h h l l x bst nop (bank active after t rcd ) lhlhl ba, ca, ap read/reada illegal 2 l h l l l ba, ca, ap writ/writa illegal 2 l l h h l ba, ra actv illegal 6 l l h l l ba, ap pre/pall illegal 2 l l l h l x ref/self illegal lllll mode mrs illegal l l h h h ba, ra actvm illegal l h l l h ba, ca, ap bwrit/ bwrita illegal llllh special mode smrs special mode registar set write recovering /block write recovering hxxxx x desl nop (bank active after t wr /t bwc ) l h h h x x nop nop (bank active after t wr /t bwc ) l h h l l x bst nop (bank active after t wr /t bwc ) lhlhl ba, ca, ap read/reada start read ; determine ap 4 l h l l l ba, ca, ap writ/writa new write ; determine ap l l h h l ba, ra actv illegal 2 l l h l l ba, ap pre/pall illegal 2 l l l h l x ref/self illegal llllx mode/ special mode mrs/ smrs illegal l l h h h ba, ra actvm illegal l h l l h ba, ca, ap bwrit/ bwrita new block write ; determine ap
12 mb81g83222-010/mb81g83222-012/MB81G83222-015 n functional truth table (continued) operation command table (continued) current state cs ras cas we dsf addr command function notes write recovering with auto- precharge /block write recovering with auto- precharge hxxxx x desl nop (precharge after t rwl /t bwl ) l h h h x x nop nop (precharge after t rwl /t bwl ) l h h l l x bst illegal lhlhl ba, ca, ap read/reada illegal 2 l h l l l ba, ca, ap writ/writa illegal 2 l l h h l ba, ra actv illegal 2 l l h l l ba, ap pre/pall illegal 2 l l l h l x ref/self illegal llllx mode/ special mode mrs/ smrs illegal l l h h h ba, ra actvm illegal 2 l h l l h ba, ca, ap bwrit/ bwrita illegal refreshing h xxxx x desl nop (idle after t rc ) l h h x x x nop/bst nop (idle after t rc ) lhlxx x read/reada/ writ/writa/ bwrit/ bwrita illegal llhxx x actv/actvm/ pre/pall illegal lllxx x ref/self/ mrs/smrs illegal 6 mode register setting hxxxx x desl nop (idle after t rsc ) l h h h x x nop nop (idle after t rsc ) l h h l l x bst illegal lhlxx x read/reada/ writ/writa/ bwrit/ bwrita illegal l lxxx x actv/actvm/ pre/pall ref/self/ mrs/smrs illegal
13 mb81g83222-010/mb81g83222-012/MB81G83222-015 n functional truth table (continued) operation command table (continued) abbreviations : ra=row adress ba=bank address ca=column address ap=auto precharge current state cs ras cas we dsf addr command function notes special mode register setting hxxxx x desl nop (return to original state after t rsc ) lhhhx x nop nop (return to original state after t rsc ) l h h l l x bst illegal lhlxx x read/reada/ writ/writa/ bwrit/ bwrita illegal l lxxx x actv/actvm/ pre/pall ref/self/ mrs/smrs illegal
14 mb81g83222-010/mb81g83222-012/MB81G83222-015 n functional truth table (continued) command truth table for cke current state cke n-1 cke n cs ras cas we dsf addr function notes self- refresh hxxxxxx x inv alid lhhxxxx x exit self-refresh, idle after t rc l h l h h h x x exit self-refresh, idle after t rc lhlhlxx x illegal l h l l x x x x illegal l lxxxxx x nop (maintain self-refresh) self- refresh recovery hhhxxxx x idel after t rc h h l h h x x x idel after t rc hhlhlxx x illegal h h l l x x x x illegal hlhxxxx x begin clock suspend next cycle h l l h h x x x begin clock suspend next cycle h l l h l x x x illegal h l l l x x x x illegal lhxxxxx x exit clock suspend next cycle l lxxxxx x maintain clock suspend power down hxxxxxx inv alid lhxxxxx x exit power down mode ? idle l lxxxxx x nop (maintain power down mode) both banks idle hhhxxxx refer to the operation command ta b l e . hhlhxxx refer to the operation command ta b l e . hhl lhxx refer to the operation command ta b l e . h h l l l h l x auto-refresh hhllllh special mode refer to the operation command ta b l e . hhlllll mode refer to the operation command ta b l e . hlhxxxx refer to the operation command ta b l e . hllhxxx refer to the operation command ta b l e . hlllhxx refer to the operation command ta b l e . h l l l l h l x self-refresh
15 mb81g83222-010/mb81g83222-012/MB81G83222-015 n functional truth table (continued) command truth table for cke (continued) notes:1. all entries assume the cke was high during the proceeding clock cycle and the current clock cycle. 2. illegal to bank in speci?d state; entry may be legal in the bank speci?d by ba, depending on the state of that bank. 3. illegal if any bank is not idle. 4. must satisfy bus contention, bus turn around, and/or write recovery requirements. 5. nop to bank precharging or in idle state. may precharge bank spesi?d by ba (and ap). 6. t rrd must be satisfied for other bank. current state cke n-1 cke n cs ras cas we dsf addr function notes both banks idle hllllll special mode refer to the operation command ta b l e . hllllll mode refer to the operation command ta b l e . lxxxxxx x power down any state other than listed above hhxxxxx x refer to the operation command ta b l e . hlxxxxx x begin clock suspend next cycle lhxxxxx x exit clock suspend next cycle l lxxxxx x maintain clock suspend
16 mb81g83222-010/mb81g83222-012/MB81G83222-015 n functional truth table (continued) table 1. : minimum clock latency or delay time for 2 bank operation notes: 1. assume no i/o con?ct. 2. if t rp < = t ck , minimum latency is a sum of bl + cl. 3. assume output is in high-z state. 4. assume pall command dose not affect any operation on opposite bank. 5. not applicable after t rp. 6. bst command should be issued only at bl=full column. 7. bst command should be issued at bl=full column and single write mode operation. mrs t rsc t rsc t rsc t rsc t rsc smrs t rsc t rsc t rsc t rsc t rsc t rsc t rsc t rsc t rsc t rsc t rsc t rsc t rsc actv (m) 1t rrd 11111111t ras read bl-1 + t rsc *1 111 1 *1 1 *1 1 *1 1 *1 1 11 reada bl + t rp *2 bl-1 + t rsc *1 1blbl bl *1 bl *1 bl *1 bl *1 1bl bl + t rp *2 bl + t rp *2 writ bl-1 + t rsc *1 111111111t rwl writa bl-1 t rwl t rp bl-1 + t rsc 1 blblblblblbl 1 bl-1 t rwl + t rp bl-1 t rwl + t rp bl-1 t rwl + t rp bwrit t bwc 1t bwc t bwc t bwc t bwc t bwc t bwc n/a 1 t bwl bwrita t bwl + t rp t bwc 1t bwc t bwc t bwc t bwc t bwc t bwc n/a 1 t bwl t bwl + t rp t bwl + t rp bst *6 111 1 1 *7 11n/a11 pre t rp *3 t rp *1 111111 1 *7 111 t rp *3 t rp *3 pall *4 t rp *3 t rp *1 t rp n/a *5 n/a *5 t rp *3 t rp *3 ref t rc t rc t rp t rrd t rc self t pde + t rc t pde + t rc t pde + t rc t pde + t rc t pde + t rc second command (opposite bank) first command mrs smrs actv (m) read reada writ writa bwrit bwrita bst pre pall ref self illegal command *6
17 mb81g83222-010/mb81g83222-012/MB81G83222-015 cke\ write/block write with auto precharge fig. 2 - state diagram (one bank operation) cke\ cke bank active suspend mode register set idle bank active write or block write read pre- charge read suspend write suspend power on power down auto- refresh self- refresh cke cke\(pd) ref selfx self mrs writ read read pre or pall power applied definition of allows manual input automatic sequence pre or pall write suspend read with auto precharge read suspend reada writa reada writa pre or pall pre or pall bst bst reada writa read writ writ special mode register set smrs smrs bwrit bwrita bwrit bwrita actv or actvm bwrit bwrita cke\ cke cke\ cke cke cke\ cke
18 mb81g83222-010/mb81g83222-012/MB81G83222-015 n functional description sdram basic function five major differences between this sgram and conventional drams are: synchronized operation, burst mode, mode register, write per bit, and block write. the synchronized operation is the fundamental difference. an sgram uses a clock input for the synchronization, where the dram is basically asynchronous memory even if it has been using two clocks, ras and cas . each operation of dram is determined by their timing phase difference while each operation of sgram is determined by commands and all operations are referenced by a positive clock edge. fig. 4 in page 23 show the basic timing diagram difference. the burst mode is a very high speed access mode utilizing an internal column address generator. once a column addresses for the ?st access is set, following addresses are automatically generated by the internal column address counter. the mode register is to justify the sgram operation and function into desired system conditions. referenced in mode register table, if a system requires interleave for burst type and two clocks for cas latency, sdram can be con?ured to those conditions by mode register programming. the write per bit function is to enable selective write operation for each 32 bit i/o. this function is activated by actvm command for each bank. the block write function enables writing the same data (logic 0 or 1) into all of the memory cells for eight successive column (8 32 bit) within a selected row. clock (clk) and clock enable (cke) all input and output signals of sgram use register type buffers. a clk is used as a trigger for the register and internal burst counter increment. all inputs are latched by a positive edge of clk. all outputs are validated by the clk. cke is a high active clock enable signal. when cke = low is latched at a clock input during active cycle, the next clock will be internally masked. during idle state (all banks have been precharged), cke = low enters the power down mode(standby) and this will make extremely low standby current. chip select (cs ) cs enables all commands inputs, ras , cas , we , dsf and address input. when cs is high level, command signals are negated but internal operation such as burst cycle will not be suspended. in the small system cs can be tied to ground level. command input (ras , cas we , and dsf) unlike a conventional dram, ras , cas , we , and dsf do not directly imply sgram operation, such as row address strobe by ras . instead, each combination of ras , cas , we , and dsf input in conjunction with cs input at a rising edge of the clk determines sgram operation. refer to function truth table in page 5. address input (a 0 to a 8 ) address input selects an arbitrary location of a total of 131,072 words of each memory cell matrix. a total seventeen of address input signals are required to decode such a matrix with nine row and eight column address format. sdram adopts an address multiplexer in order to reduce the pin count of the address line. at a bank active command (actv or actvm), nine row addresses are initially latched and the remainder of eight column addresses are then latched by a column address strobe command of either a read command (read or reada) or write command (writ, writa, bwrit, or bwrita). the a 8 /ap pin determines precharge option. refer to precharge and precharge option in page 21. bank select (a 9 ) this sgram has two banks and each bank is organized as 128k-words by 32-bit. bank selection by a 9 occurs at bank active command (actv or actvm) followed by read (read or reada), write (writ, writa, bwrit, or bwrita), and precharge command (pre).
19 mb81g83222-010/mb81g83222-012/MB81G83222-015 n functional description (continued) data input and output (dq 0 to dq 31 ) input data is latched and written into memory at the clock followed by a write command input. data output is obtained by the following conditions followed by a read command input: t rac ; from the bank active command when t rcd (min.) is satisfied. (this parameter is reference only.) t cac ; from the read command when t rcd is greater than t rcd (min.). t ac ; from the clock edge after t rac and t cac . the polarity of the output data is identical to that of the input. valid data time is between access time (determined by the three conditions above) and the next positive clock edge (t oh ). data i/o mask (dqm0 to dqm3) dqm 0 to dqm 3 are an active high enable input and have an output disable and input mask function. during burst cycle and when dqm 0 3 = high is latched by a clock, input is masked at the same clock (write&block write operation) and output will be masked at the second clock later (read operation) while internal burst counter will increment by one or will go to the next stage depending on burst type. dqm 0 , dqm 1 , dqm 2 , and dqm 3 controls dq 0 to dq 7 , dq 8 to dq 15 , dq 16 to dq 23 , and dq 24 to dq 31 , respectively. burst mode operation and burst type the burst mode provides faster memory access. the burst mode is implemented by keeping the same row address and by automatic strobing column address. access time and cycle time of burst mode is specified as t ac and t ck , respectively. the internal column address counter operation is determined by a mode register which defines burst type and burst count length from 1 bits to full column of boundary. in order to terminate or to move from the current burst mode to the next stage while the remaining burst count is more than 1, the following combinations will be required: current stage next stage method (assert the following command) burst read burst read read command burst read burst write 1st step mask command (normally 3 clock cycles) 2nd step write command after l owd burst write burst write write command burst write burst read read command burst read precharge precharge command burst write precharge 1st step mask command 2nd step precharge command after t rwl
20 mb81g83222-010/mb81g83222-012/MB81G83222-015 n functional description (continued) burst mode operation and burst type (continued) when the full burst operation is executed at single write mode, auto-precharge command is valid only at write operation. the burst type can be selected either sequential or interleave mode. but only the sequential mode is usable to the full column burst. the sequential mode is an incremental decoding scheme within a boundary address to be determined by burst length, it assigns +1 to the previous (or initial) address until reaching the end of boundary address and then wraps round to least signi?ant address(=0). full column burst and burst stop command (bst) the full column burst is an option of burst length and available only at sequential mode of burst type. this full column burst mode is repeatedly access to the same column. if burst mode reaches end of column address, then it wraps round to ?st column address (=0) and continues to count until interrupted by the news read (read) /write (writ/ bwrit) , precharge (pre) , or burst stop (bst) command. the selection of auto-precharge option is illegal during the full column burst operation except write command at burst read & single write mode. the bst command is applicable to terminated the full column burst operation and illegal during the burst operation with length of 1, 2, 4, and 8. if the bst command is asserted during the full column burst mode, its operation is terminated immediately and the internal state moves to bank active. when read mode is interrupted by bst command, the output will be in high-z. for the detail rule, please refer to timing diagram-8. when write mode is interrupted by bst command, the data to be applied at the same time with bst command will be ignored. burst read & single write the burst read and single write mode provides single word write operation regardless of its burst length. in this mode, burst read operation does not be affected by this mode. burst length starting column address a 2 a 1 a 0 sequential mode interleave 2 x x 0 0 ?1 0 ?1 x x 1 1 ?0 1 ?0 4 x 0 0 0 ?1 ?2 ?3 0 ?1 ?2 ?3 x 0 1 1 ?2 ?3 ?0 1 ?0 ?3 ?2 x 1 0 2 ?3 ?0 ?1 2 ?3 ?0 ?1 x 1 1 3 ?0 ?1 ?2 3 ?2 ?1 ?0 8 0 0 0 0 ?1 ?2 ?3 ?4 ?5 ?6 ?7 0 ?1 ?2 ?3 ?4 ?5 ?6 ?7 0 0 1 1 ?2 ?3 ?4 ?5 ?6 ?7 ?0 1 ?0 ?3 ?2 ?5 ?4 ?7 ?6 0 1 0 2 ?3 ?4 ?5 ?6 ?7 ?0 ?1 2 ?3 ?0 ?1 ?6 ?7 ?4 ?5 0 1 1 3 ?4 ?5 ?6 ?7 ?0 ?1 ?2 3 ?2 ?0 ?1 ?7 ?6 ?5 ?4 1 0 0 4 ?5 ?6 ?7 ?0 ?1 ?2 ?3 4 ?5 ?6 ?7 ?0 ?1 ?2 ?3 1 0 1 5 ?6 ?7 ?0 ?1 ?2 ?3 ?4 5 ?4 ?7 ?6 ?1 ?0 ?3 ?2 1 1 0 6 ?7 ?0 ?1 ?2 ?3 ?4 ?5 6 ?7 ?4 ?5 ?2 ?3 ?0 ?1 1 1 1 7 ?0 ?1 ?2 ?3 ?4 ?5 ?6 7 ?6 ?5 ?4 ?3 ?2 ?1 ?0
21 mb81g83222-010/mb81g83222-012/MB81G83222-015 n functional description (continued) precharge and precharge option (pre, pall) sgram memory is the same as dram, requiring precharge and refresh operations. precharge rewrites the bit line and to reset the internal row address line and is executed by precharge command (pre). with the precharge command, sgram will automatically be in idle state after precharge time (t rp ). the precharged bank is selected by combination of a 8 and a 9 when precharge command is asserted. if a 8 = high, both banks are precharged regardless of a 9 (pall). if a 8 = low, a bank to be selected by a 9 is precharged (pre). the auto precharge enters precharge mode at the end of burst mode of read or write without precharge command assertion. this auto precharge is entered by a 8 =high when a read or write command is asserted. refer to function truth table. write per bit operation (actvm) the write per bit (wpb) is a function to enable selective write operation for each dq pin. bank active & wpb enable command (actvm) enables wpb operation for the associated bank and actv command disables it. selection of masking i/o should be stored in load mask register (dqi=high : write enable, dqi=low : write mask) by smrs command with as=high. for example, if a mask register bit=low, the associated data bit is masked when a write command is excused and wpb has been enabled for the bank being written. wpb is applicable to either burst writes, single writes, and block writes. dqm masking is applicable for wpb as well as non-write-per-bit. actvm is valid until the associated bank is precharged. block write operation (bwrit, bwrita) this command enables to write the same data (logic 0 or 1) in a selected block of eight successive columns (8 32 bits) during a single access cycle. the column block is selected by a 3 to a 7 of column address input, and a 0 , a 1 , and a 2 are ignored and the data to be written is stored in color register by smrs command with a 6 =high. column data masking is provided on an individual column basis for each byte of data. the column mask is driven on the dq pins during block write command. the dq column mask function is segmented on a per byte basis (i.e. dq 0 7 provides the column mask for data byte 0-7, dq 8 - 15 , and so on.). a dq column mask of h enables the particular column to be written while a value of l disables writing of the data. the relationship between dq bits and column within the block is logically equivalent within each byte (i.e. dq0 masks column? for data bits [0-7], dq 8 masks column? for data bits [8-15], dq 1 masks column? for data bits [0-7], dq 9 masks column ? for data bits [8-15], and so on). i/o mask register 0 : write mask 1 : write enable dq input for column masking 0 : write mask 1 : write enable 0101 01 0 0 0 1 1 1 0 0 01 1 10 0 01 1 1 0101 01 0 4 3 2 6 7 5 1 0123 67 01 1 0 45 1 1 1 1 1 0 0 0 dq 0 dq 4 dq 3 dq 2 dq 6 dq 7 dq 5 dq 1 1111 11 0 0 0101 01 0 1 color register memory cell selected by row addr : a 0 -a 8 column addr : a 3 -a 7 :masked bit by i/o & column masking (color data is not written in this memory cell.) fig. 3 - block write & write per bit operation (example for dq 0 - 7 ) note: same organization for every bytes (dq 0 - 7 , dq 8 - 15 , dq 16 - 23 , dq 24 - 31 ). column address i/o number
22 mb81g83222-010/mb81g83222-012/MB81G83222-015 n functional description (continued) block write operation (bwrit, bwrita) (continued) the block write is always non-burst, independent of the burst length and burst type that has been programmed into the mode register. back-to-back block write operation is allowed with the block write cycle time (t bwc ) is satisfied. if wpb was enabled to the bank by actvm command, then write-per-bit masking of the color register data is enabled. if wpb was disabled, the write per bit masking of the color register data is disabled. when wpb is enabled, the data in the color register (accessed via special register access), is masked by the data in the mask register (accessed via special register access), a mask register bit=high enables the associated data bit to be written and mask bit=low disables the associated data bit from being written. dqm masking provides independent data byte masking during block write exactly the same as it dose during normal write operations, except that the control is extended to the 8 consecutive columns of the block. auto-refresh (ref) auto-refresh uses the internal refresh address counter. the sgram auto-refresh command (ref) generates precharge command internally. all banks of sgram should be precharged prior to the auto-refresh command. the auto-refresh command should also be asserted every 16 m s or a total 1,024 refresh commands within a 16.4 ms period. self-refresh entry (self) self-refresh function provides automatic refresh by an internal timer as well as auto-refresh and will continue the refresh function until cancelled by self-refresh exit command (selfx). the self-refresh is entered by applying an auto-refresh command in conjunction with cke = low (self). once sgram enters the self-refresh mode, all inputs except for cke will be ?on? care (either logic high or low level state) and outputs will be in a high-z state. during a self-refresh mode, cke = low should be maintained. note that a total of 1,024 auto-refresh commands within 1 ms must be asserted prior to the self-refresh mode entry. self-refresh exit (selfx) to exit self-refresh mode, apply minimum 4 clock cycle before cke brought high, and then the nop command (nop) or deselect command (desl) should be asserted within one t rc period. refer to timing diagram for the detail. it is recommended to assert an auto-refresh command just after the t rc period to avoid the violation of refresh period. note that a total of 1,024 auto-refresh commands within 1 ms must be asserted after the self-refresh exit. mode register set (mrs) the mode register of sgram provides a variety of different operations. the register consists of ?e operation ?lds; burst length, burst type, cas latency, test mode, and operation code. refer to mode register table in page 33. the mode register can be programmed by the mode register set command (mrs). each ?ld is set by the address line. once a mode register is programmed, the contents of the register will be held. the condition of the mode register is unde?ed after the power-up stage. it is required to set each ?ld after initialization of sgram. refer to power-up initialization below. special mode regester set (smrs) the special mode register set command (smrs) is applicable to set the color register for block write operation or to set the mask register for write per bit operation. color register and mask register is determined by the input level of a 6 and a 5 respectively, and it is illegal to determine both color register and mask register within one command (a 6 =a 5 =h is illegal). the data to be stored in color register or mask register is input via dq pins. the smrs command can be valid during idle or bank active state. both color register and mask register are not cleared or reset until changed by another smrs cycle (or part loses power). refer to the special mode register table in page 33.
23 mb81g83222-010/mb81g83222-012/MB81G83222-015 n functional description (continued) power-up initialization the sgram internal condition after power-up will be unde?ed. it is required to follow the following power on sequence to execute read or write operation. 1. apply power and start clock. attempt to maintain either nop or desl command at the input. 2. maintain stable power, stable clock, and nop condition for a minimum of 200 m s. 3. precharge all banks by precharge (pre) or precharge all command (pall). 4. assert minimum of 8 auto-refresh command(ref). 5. program the mode register by mode register set command(mrs). in addition, it is recommended dqm 0 - 3 and cke to track v cc to insure that output is high-z state. the mode register set command (mrs) can be set before 8 auto-refresh command (ref).
24 mb81g83222-010/mb81g83222-012/MB81G83222-015 fig. 4 - basic timing for conventional dram vs synchronous graphic ram ras cas dq clk cs dq t cms t cms ras cas cke we cas latency=1 burst length=4 active read/write precharge address hh h dsf t cmh t cmh t as t ah h : read l : write ba (a 9 ) ra ba (a 9 ) ca ba (a 9 ) ap (a 8 ) row adress select column address select precharge
25 mb81g83222-010/mb81g83222-012/MB81G83222-015 n capacitance (t a = 25 c, f = 1 mhz) n recommended operating conditions (referenced to v ss ) notes:1. overshoot limit : v ih (max.)=v cc +1.3 v with a pullsewidth 5 ns. 2. undershoot limit: : v il (min.)= ?.3 v with a pullsewidth 5 ns. parameter symbol typ. max. unit input capacitance, address c in1 ?pf input capacitance, except for address c in2 ?pf i/o capacitance c i/o ?pf parameter notes symbol min. typ. max. unit supply voltage v cc , v ccq 3.0 3.3 3.6 v v ss , v ssq 000v input high voltage 1 v ih 2.0 v cc + 0.3 v input low voltage 2 v il ?.3 0.8 v ambient temperature t a 070 c
26 mb81g83222-010/mb81g83222-012/MB81G83222-015 n dc characteristics (recommended operating conditions unless otherwise noted.) notes 1, 2 parameter symbol conditions value unit min. max. output high voltage v oh (dc) i oh = ? ma 2.4 v output low voltage v ol (dc) i ol = 2 ma 0.4 v input leakage current (any input) i li 0 v v in v cc ; all other pins not under test = 0 v ?0 10 m a output leakage current i lo 0 v v in v cc ; data out disabled ?0 10 m a operating current (average power supply current) mb81g83222-010 i cc1s no burst : t ck = min. t rc = min. one bank active 185 ma mb81g83222-012 160 MB81G83222-015 140 mb81g83222-010 i cc1d no burst : t ck = min. t rc = min. all banks active 280 ma mb81g83222-012 245 MB81G83222-015 210 precharge standby current (power supply current) i cc2p cke = v il all banks idle t ck = min. power down mode ?ma mb81g83222-010 i cc2n cke = v ih all banks idle t ck = min. 70 ma mb81g83222-012 65 MB81G83222-015 55 active standby current (power supply current) i cc3p cke = v il any banks active t ck = min. ?5ma mb81g83222-010 i cc3n cke = vi h any banks active t ck = min. 75 ma mb81g83222-012 70 MB81G83222-015 60 burst mode current (average power supply current) mb81g83222-010 i cc4 t ck = min. 250 ma mb81g83222-012 210 MB81G83222-015 175 refresh current #1 (average power supply current) mb81g83222-010 i cc5s auto-refresh; t ck = min. t rc =min. 155 ma mb81g83222-012 135 MB81G83222-015 120 refresh current #1 (average power supply current) mb81g83222-010 i cc5d auto-refresh; t ck = min. t rc =min. t rrd = min. 235 ma mb81g83222-012 205 MB81G83222-015 175
27 mb81g83222-010/mb81g83222-012/MB81G83222-015 n dc characteristics (continued) (recommended operating conditions unless otherwise noted.) notes 1, 2 n ac characteristics (recommended operating conditions unless otherwise noted.) notes 2, 3, 4 parameter symbol conditions value unit min. max. refresh current #2 (average power supply current) i cc6 self-refresh; cke = v il ?ma block write current (average power supply current) mb81g83222-010 i cc7 block write; t bwc = min. 165 ma mb81g83222-012 140 MB81G83222-015 115 parameter notes symbol mb81g83222-010 mb81g83222-012 MB81G83222-015 unit min. max. min. max. min. max. clock period cas latency=1 t ck 30 35 40 ns cas latency=2 15 17.5 20 ns cas latency=3 10 12 15 ns clock high time t ch 3.5??ns clock low time t cl 3.5??ns data-in setup time t ds 3 3.5 3.5 ns data-in hold time t dh 1 1.5 1.5 ns address setup time t as 3 3.5 3.5 ns address hold time t ah 1 1.5 1.5 ns cke setup time t cks 3 3.5 3.5 ns cke hold time t ckh 1 1.5 1.5 ns command setup time (cs , ras , cas , we , dsf, dqm) t cms 3 3.5 3.5 ns command hold time (cs , ras , cas , we , dsf, dqm) t cmh 1 1.5 1.5 ns access time from clock (t ck =min.) cas latency=1 t ac 28 32 35 ns cas latency=2 13 14.5 16 ns cas latency=3 9 11 12 ns output in low-z t lz 3??ns output in high-z 7 cas latency=1 t hz 420424430ns cas latency=2 4 15 4 17.5 4 20 ns cas latency=3 4 10 4 12 4 15 ns output hold time t oh 4??ns time between refresh t ref 16.4 16.4 16.4 ms transition time t t 0.5 30 0.5 30 0.5 30 ns power down exit time t pde 12?4?7ns 5, 6
28 mb81g83222-010/mb81g83222-012/MB81G83222-015 n ac characteristics (continued) (recommended operating conditions unless otherwise noted.) notes 2, 3, 4 base values for clock count/latency clock count formula note 13 latency - fixed values (the latency values on these parameters are ?ed regardless of clock period.) parameter notes symbol mb81g83222-010 mb81g83222-012 MB81G83222-015 unit min. max. min. max. min. max. ras cycle time 8 t rc 90 106 125 ns ras access time 9 t rac ?8?7?5ns cas access time 10, 13 t cac ?8?2?5ns ras precharge time t rp 30?6?5ns ras active time t ras 60 100000 70 100000 80 100000 ns ras to cas delay time 11 t rcd 30?5?0ns write recovery time t wr 10?2?5ns write to precharge delay time t rwl 15 17.5 20 ns block write to precharge delay time t bwl 20?4?0ns ras to ras bank active delay time t rrd 20?4?0ns block write cycle time t bwc 20?4?0ns mode and special mode register cycle time t rsc 20?4?0ns parameter notes symbol mb81g83222- 010 mb81g83222- 012 mb881g83222- 015 unit cke to clock disable i cke 1 1 1 cycle dqm to output in high-z i dqz 2 2 2 cycle dqm to input data delay i dqd 0 0 0 cycle last output to write command delay i owd 2 2 2 cycle write command to input data delay i dwd 0 0 0 cycle precharge to output in high-z delay cl = 1 i roh 1 1 1 cycle cl = 2 2 2 2 cycle cl = 3 3 3 3 cycle burst stop command to output in high-z delay cl = 1 i bsh 1 1 1 cycle cl = 2 2 2 2 cycle cl = 3 3 3 3 cycle cas to cas delay (min.) i ccd 1 1 1 cycle cas bank delay (min.) i cbd 1 1 1 cycle clock 3 clock period base value (round off a whole number)
29 mb81g83222-010/mb81g83222-012/MB81G83222-015 notes:1. i cc depends on the output termination or load conditions, clock cycle rate, and signal clocking rate; the specified values are obtained with the output open and no termination register. 2. an initial pause (desl or nop) of 200 m s is required after power-up followed by a minimum of eight auto-refresh cycles. 3. ac characteristics assume t t = 1 ns and 30 pf of capacitive load. 4. 1.4v is the reference level for measuring timing of input signals. transition times are measured between v ih (min.) and v il (max.). 5. assumes t rcd and t cac are satisfied. 6. t ac also specifies the access time at burst mode except for first access. 7. speci?d where output buffer is no longer driven. 8. actual clock count of t rc (l rc ) will be sum of clock count of t ras (l ras ) and t rp (l rp ). 9. t rac is a reference value. maximum value is obtained from the sum of t rcd (min.) and t cac (max.). 10. assumes t rac and t ac are satisfied. 11. operation within the t rcd (min.) ensures that t rac can be met; if t rcd is greater than the specified t rcd (min.), access time is determined by t cac or t ac . 12. all base values are measured from the clock edge at the command input to the clock edge for the next command input. all clock counts are calculated by a simple formula: clock count equals base value divided by clock period (round off to a whole number). 13. the l cac is programmed by the mode register.
30 mb81g83222-010/mb81g83222-012/MB81G83222-015 fig. 5 - example of ac test load circuit r 1 =50 w c l =30 pf lvttl output 1.4 v note: ac characteristics are measured in this condition. this load circuits are not applicable for v oh and v ol .
31 mb81g83222-010/mb81g83222-012/MB81G83222-015 fig. 6 - timing diagram, setup, hold and delay time clk cke t pde (min.) nop don? care don? care command fig. 7 - timing diagram, delay time for power down exit 1 clock (min.) nop actv t ds , t as , t cks , t cms t ch t ck t ac t hz t oh t lz t cl clk input (control, add. & data) output 2.0 v 1.4 v 0.8 v 1.4 v 2.4 v 0.4 v 1.4 v 2.0 v 0.8 v note: reference level of input signal is 1.4 v for lvttl. access time is measured at 1.4 v for lvttl. t dh , t ah , t ckh , t cmh
32 mb81g83222-010/mb81g83222-012/MB81G83222-015 t pde , t rp , t ras , t rcd , t rwl , t bwl , t rrd , t bwc , t rsc command command clk input (control) fig. 8 - timing diagram, pulse width note: this parameter is a limit value of the rising edge of the clock from one command input to next input. t pde is the latency value from the rising edge of cke. measurement reference voltage is 1.4 v. fig. 9 - timing diagram, access time t rac t cac clk ras cas dq (output) note: t rac is a reference value. data can be obtained after both t cac and t ac are satis?d. t rcd q(valid) (cas latency - 1) x t ck t ac
33 mb81g83222-010/mb81g83222-012/MB81G83222-015 n mode register table mode register set address op- code 0 0 cl bt bl mode register burst length 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 1 2 4 8 reserved reserved reserved full column 0 1 0 1 0 1 0 1 burst type sequential (wrap round, binary-up) interleave (wrap round, binary-up) 0 1 cas latency 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 reserved 1 2 3 reserved reserved reserved reserved 0 1 0 1 0 1 0 1 op-code burst read & burst write burst read & single write 0 1 note: when a 9 =1, burst length at write is always one regardless of bl value. 00 0 special mode register special mode register set 0 lc lm 0 000 load mask register 0 1 load color register 0 1 disable enable disable enable 1 2 4 8 reserved reserved reserved reserved bt=0 bt=1 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a 2 a 1 a 0 a 6 a 5 a 4 a 3 a 9 a 6 a 5 address a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0
34 mb81g83222-010/mb81g83222-012/MB81G83222-015 timing diagram-1 : clock enable - read and write suspend (@ bl = 4) q1 q2 (no change) q3 (no change) q4 d1 not written d2 not written d3 d4 clk cke clk (internal) dq (read) dq (write) notes: 1. the latency of cke (l cke ) is one clock. 2. during read mode, burst counter will not be incremented/decremented at the next clock of csus command. output remain the same data. 3. during the write mode, data at the next clock of csus command is ignored. 1 2 1 2 3 3 2 2 nop pd(nop) don? care nop actv clk cke command timing diagram-2 : clock enable - power down entry and exit notes: 1. precharge command (pre or pall) should be asserted if any bank is active and in the burst mode. 2. precharge command can be posted in conjunction with cke when burst mode is ended at this clock. 3. the actv command can be latched after t pde (min) + 1clock(min.). it is recommended to apply nop command in conjunction with cke. it is also recommended to apply minimum of 4 clocks to stabilize external clock prior to actv command. 1 23 nop 3 t pde 1 clock (min.) t ref (max.) l cke (1 clock) l cke (1 clock)
35 mb81g83222-010/mb81g83222-012/MB81G83222-015 i cbd i cbd timing diagram-3 : column address to column address input delay clk ras cas row address column address address column address column address column address i ccd column address note: cas to cas address delay can be one or more clock period. t rcd (min.) i ccd (1 clock) i ccd i ccd timing diagram-4 : different bank address input delay clk ras cas row address row address address a 9 (bs) column address column address column address column address t rrd (min.) t rcd (min.) t rcd (min.) bank 0 bank 1 bank 0 bank 1 bank 0 bank 1
36 mb81g83222-010/mb81g83222-012/MB81G83222-015 t ras (min.) timing diagram-5 : dqm - input mask and output disable (@ bl=4) clk dqm 0 3 (@ read) dq (@ read) dqm 0 3 (@ write) dq (@ write) hi-z end of burst end of burst l dqz (2clocks) q1 q2 q4 l dqd (same clock) d1 masked d3 d4 clk command actv acvtm precharge timing diagram-6 : precharge timing (applied to the same bank)
37 mb81g83222-010/mb81g83222-012/MB81G83222-015 timing diagram-7 : read interrupted by precharge (example @ cl=2, bl=4) clk command dq command dq command dq command dq q1 precharge q1 q2 q1 q2 q3 q1 q2 q3 q4 note: in case of cl=1, the l roh is 1 clock. in case of cl=2, the l roh is 2 clock. in case of cl=3, the l roh is 3 clock. precharge l roh (2 clocks) hi-z l roh (2 clocks) hi-z l roh (2 clocks) hi-z no effect (end of burst) precharge precharge
38 mb81g83222-010/mb81g83222-012/MB81G83222-015 timing diagram-8 : read interrupted by burst stop (example @ bl=full column) timing diagram-9 : write interrupted by burst stop (example @ cl=2) clk command (cl=1) dq command (cl=2) dq command (cl=3) dq hi-z qn qn qn+ 1 hi-z hi-z note: the bst command is applicable to terminated the full column burst operation. the selection of auto-precharge option is illegal during the full column burst operation except write command at burst read & single write mode. bst qn- 1 qn- 2 qn+ 2 qn- 1 qn- 2 qn+ 1 (1 clock) (2 clocks) bst bst l bsh l bsh qn qn- 1 qn- 2 (3 clocks) l bsh clk command dq last data-in masked by bst bst command note: the burst stop command is applicable only to full column burst operation.
39 mb81g83222-010/mb81g83222-012/MB81G83222-015 t rwl (min.) t rp (min.) timing diagram-10 : write interrupted by dqm0~3 & precharge (example @ cl=2) clk command dq actv actvm last data-in masked by dqm masked by pre note: the precharge command (pre) should only be issued after the t rwl of ?al data input is satis?d. pre timing diagram-11 : read interrupted by write (example @ cl=2, bl 3 4) clk command dq data out masked data in data in writ read notes: 1. first dqm 0 3 makes high impedance state (hi-z) between last output and ?st input data. 2. second dqm 0 3 makes internal output data mask to avoid bus contention. 3. third dqm 0 3 in illustrated above also makes internal output data mask. if burst read ends (?al data output) at or after the second clock of burst write, this third dqm 0 3 is required to avoid internal bus contention. i dwd (same clock) l owd (2 clocks) note 1 note 2 note 3 l dqz (2 clocks) dqm 0 to dqm 3 dqm 0 to dqm 3
40 mb81g83222-010/mb81g83222-012/MB81G83222-015 timing diagram-12 : write interrupt by read timing (example @ cl=3, bl>2) timing diagram-13 : block write timing clk command dq note: read command can be asserted at the next cycle of write command. the write data after read command is masked by read command. read d1 q1 q2 d2 masked by read writ dqm 0 to dqm 3 t wr (min.) t cac (min.) clk command dq bwrit note: dq inputs are used for column masking. (dq=h : write enable, dq=l : masked) write data is set by smrs (load color register) command. nop or desl column masking column masking bwrit dqm 0 to dqm 3 t bwc (min.)
41 mb81g83222-010/mb81g83222-012/MB81G83222-015 timing diagram-14 : write per bit timing timing diagram-15 : block write to read/write timing (example @ cl=2, bl 3 2) clk command dq actvm note: wpb is available for the bank activated by actvm command. mask data (mask enable/disable) is set by smrs (load mask register) command. q1 actv q2 writ writ wpb enable wpb disable a 9 (ba) t rrd (min.) t rcd (min.) t rcd (min.) clk command dq q1 q2 bwrit note: read/write command can be asserted after t bwc from block write command. dqm 0 to dqm 3 column masking read (or writ) nor or desl t bwc
42 mb81g83222-010/mb81g83222-012/MB81G83222-015 timing diagram-16 : read with auto-precharge (example @ cl=2, bl=2 applied to same bank) timing diagram-17 : write with auto-precharge (example @ cl=2, bl=2 applied to same bank) clk command dq reada note: precharge at read with auto-precharge command (reada) is started from number of clocks that is the same as burst length after reada command is asserted. actv nop or desl dqm 0 to dqm 3 actv q1 q2 t ras (min.) 2 clocks (same value as bl) t rp (min.) note: precharge at write with auto-precharge is started after the t rwl from the end of burst. even if the ?al data is masked by dqm 0 3 , the precharge does not start the clock of ?al data input. once auto precharge command is asserted, no new command within the same bank can be issued. auto-precharge command doesn? affect at full column burst operation except burst read & single write mode. clk command dq writa actv nop or desl dqm 0 to dqm 3 actv t ras (min.) - t rwl (min.) d1 d2 t rwl (min.) + t rp (min.)
43 mb81g83222-010/mb81g83222-012/MB81G83222-015 column masking timing diagram-18 : block write to precharge timing clk command dq pre actv note: the precharge command (pre) should only be asserted after the t bwl from last block write command is satis?d. dqm 0 to dqm 3 bwrit nop or desl t bwl (min.) t rp (min.) timing diagram-19 : block write with auto-precharge(applied to same bank) clk dq nop or desl actv dqm 0 to dqm 3 column masking command note: precharge at write with auto-precharge is started after the t bwl from the bwrita command. once auto precharge command is asserted, no new command within the same bank can be asserted. auto-precharge command doesn? affect at full column burst operation. bwrita actv t ras (min.)-t bwl (min.) t bwl (min.)+t rp (min.)
44 mb81g83222-010/mb81g83222-012/MB81G83222-015 timing diagram-20 : auto-refresh timing clk command a 9 (ba) ref command ref don? care ba 1 nop nop ref nop 5 34 notes: 1. all banks should be precharged prior to the ?st auto-refresh command (ref). 2. bank select is ignored at ref command. the refresh address and bank select are selected by internal refresh counter. 3. either nop or desl command should be asserted during t rrd and t rc period while auto-refresh mode. 4. the second ref command can be asserted after t rrd from the ?st ref command because the second ref command select the other bank. 5. any activation command such as actv or mrs command other than ref command should be asserted after t rc from the last ref command. t rrd (min.) t rc (min.) t rc (min.) don? care don? care timing diagram-21 : self-refresh entry and exit timing clk cke command nop notes: 1. precharge command (pre or pall) should be asserted if any bank is active prior to self-refresh entry command (self). 2. the self-refresh exit command (selfx) is latched after t ped (min.). it is recommended to apply nop command in conjunction with cke. it is also recommended to apply minimum of 4 clocks to stabilize external clock prior to selfx command. 3. either nop or desl command can be used during t rc period. self don? care srex command nop 2 nop 3 1 t pde (min.) t rc (min.)
45 mb81g83222-010/mb81g83222-012/MB81G83222-015 timing diagram-22 : block write & special mode register set timing clk command dq nop desl color or mask dqm 0 to dqm 3 smrs bwrit nop desl smrs column masking color or mask notes: 1. block write command can be asserted after the t rsc from special mode register set command is satis?d. 2. special mode register set command can be asserted after t bwc from block write comand is satis?d. t bwc (min.) t rsc (min.) timing diagram-23 : special mode register set timing clk command dq smrs note: this command sets mask data or color data (depend on special mode address) for each i/o. mask data controls wpb operation (high : write enable, low : masked). color data is to be written by block write command. nop or desl command color or mask address special mode t rsc (min.)
46 mb81g83222-010/mb81g83222-012/MB81G83222-015 timing diagram-24 : mode register set timing clk command address mrs note: the mode register set command (mrs) should be only asserted after all banks have been precharged. nop or desl mode row address actv t rsc (min.)
47 mb81g83222-010/mb81g83222-012/MB81G83222-015 n package dimensions (suf?: -pq) index (stand off) 0(0)min 3.15(.124)max (.614.016) 15.600.40 ref 12.35(.486) (.006.002) 0.150.05 (.677.016) 17.200.40 (.551.008) 14.000.20 21.600.40(.850.016) 18.85(.724)ref 0.10(.004) "a" typ 0.65(.0256) 0.13(.005) m (.012.004) 0.300.10 23.200.40(.913.016) 20.000.20(.787.008) 80 51 100 81 50 31 30 1 details of "a" part 0.25(.010) 0.30(.012) 0.53(.021)max 0.18(.007)max details of "b" part 0~10 (.031.008) 0.800.20 1995 fujitsu limited f100025s-2c-1 c dimensions in mm(inches). 100 pin, plastic qfp (fpt-100p-m15)
24 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3763 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 f9703 fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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